doc.# dsfp-hv7100 b072413 hv7100 features ? high-side drive allows use of tachs ? direct interface to host controller ? noise-immune linear speed control ? 4-bit digital speed control ? operates from single +24/+48v supply ? programmable pwm frequency ? undervoltage loc kout applications ? 24/48v chassis cooling tray ? servers ? san equipment ? cellular and fx wireless systems ? 24/48v pbx system ? base stations general description the hv7100 is an integrated pwm speed controller for driving 24 and 48vdc fans. the features and benefts provided by the hv7100 make driving fans simple and low cost. the hv7100 drives a high side external p-channel fet, allowing the use of fans having a ground-based tachometer signal. it has a wide input voltage range of +16 to +90v, ideal for +24 or +48v systems. no low voltage supply is needed. a 4-bit digital control input provides direct interfacing with a micro controller or system processor to control the fan speed. it can also be used as a stand-alone fan controller, via a thermistor connection to the linear control pin. the hv7100 has a wide pwm frequency range. when driving fans directly with a pwm supply voltage, frequency may be set low, around 50 - 120hz. when used to drive fans requiring a dc supply, an lc flter may be employed. in this case, pwm frequency may be as high as 100khz, reducing component sizes in the flter. the hv7100 is an ideal device to incorporate in fan trays and fan control modules, as it reduces circuit complexity and minimizes parts count and overall cost for thermal management. typical application circuit 24/48v fan driver/controller with high-side drive v pp host controller din0 - din3 en vgate out gnd vdd vpp1 hv7100 lin ct rt tach signals speed control enable vpp2 optional lc filter for providing a dc fan drive supertex inc. supertex inc. www .supertex.com
2 doc.# dsfp-hv7100 b072413 hv7100 absolute maximum ratings parameter value v pp to gnd -0.5v to 90v v dd to gnd -0.3v to +6v input voltage, lin -0.3v to (v dd + 0.3v) input voltage, d in 0 - d in 2 -0.3v to (v dd + 0.3v) gate to v pp +0.5v to -15v continuous power dissipation (t a = +25c) 750mw operating temperature range -40c to +85c storage temperature range -65c to +150c sym parameter min typ max units conditions electrical characteristics (operating specifcations are at t a = 25c, v pp = 16 to 75v, v dd = 3.0 to 5.5v, unless otherwise noted) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifcations is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supplies i pp v pp supply current - - 4.0 ma no ext load on v dd , f osc = 50khz, 250pf on out pin uv pp(on) v pp uvlo turn-on threshold 11.7 13.0 14.3 v --- uv pp(hys) v pp uvlo hysteresis 1.5 2.0 2.5 v --- v dd v dd internal regulation 3.0 3.3 3.6 v v pp = 16v to 75v sym parameter min typ max units v dd externally applied v dd 3.7 - 5.5 v v pp high voltage supply 16 - 75 v f osc oscillator frequency 50 - 100 khz r t oscillator timing resistor 12 - 500 k? recommended operating conditions pin confguration product marking y = last digit of year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = ?green? packaging *may be part of top marking top marking bottom marking hv7100ng yww llllllll ccccccccc aaa 1 2 3 4 5 6 7 14 13 12 11 10 9 8 out vpp2 vpp1 vga te rt ct gnd vdd lin din0 din1 din2 din3 en 14-lead soic (top view) 14-lead soic package may or may not include the following marks: si or ordering information part number package packing hv7100ng-g 14-lead soic (nb) 53/tube hv7100ng-g m903 14-lead soic (nb) 2500/reel typical thermal resistance package ja 44-lead plcc 37 o c/w -g denotes a lead (pb)-free / rohs compliant package supertex inc. www .supertex.com
3 doc.# dsfp-hv7100 b072413 hv7100 i dd(int) v dd supply current - - 2.0 ma external applied v dd = 5.0v, f osc = 50khz i dd(ext) current available from internal v dd regulator for external circuitry - - 2.0 ma ?v dd <200mv gate driver v gate gate regulator output voltage -10.2 -12 -13.8 v referenced to v pp v outh gate drive output voltage high -10.2 -12 -13.8 v referenced to v pp , test current = 15ma v outl gate drive output voltage low 0 - -0.8 v r src pull-up resistance - - 25 ? test current = 15ma r sink pull-down resistance - - 25 ? test current = -15ma t rise rise time - - 100 ns c load = 250pf t fall fall time - - 100 ns c load = 250pf oscillator f osc oscillator frequency 51 60 69 hz c t = 100nf, r t = 43.0k? f osc oscillator frequency 34 40 46 khz c t = 330pf, r t = 19.5k? logic and linear inputs v din0-3 (hi), v en (hi) logic input voltage, high 0.7 x v dd - - v --- v din0-3 (lo), v en (lo) logic input voltage, low - - 0.3 x v dd v --- t en(on) enable to gate turn on delay 0 - 150 ns lin = v dd , d in 0 - d in 3 = 1111 t en(off) enable to gate turn off delay 0 - 150 ns lin = v dd , d in 0 - d in 3 = 1111 i din0-3 digital input pull down resistance 200 330 460 k? --- i lin linear control input current -1.0 - 1.0 ua -40c to +85c duty cycle d duty cycle 16 20 24 % v lin = 0.9v, d in = 0000 d duty cycle 75 80 85 % v lin = 2.1v, d in = 0000 d duty cycle 16 20 24 % v lin = 0v, d in = 0011 d duty cycle 75 80 85 % v lin = 0v, d in = 1100 d duty cycle - - 0 % v lin = 0v, d in = 0000 d duty cycle 100 - - % v lin = 0v, d in = 1111 sym parameter min typ max units conditions electrical characteristics (cont.) (operating specifcations are at t a = 25c, v pp = 16 to 75v, v dd = 3.0 to 5.5v, unless otherwise noted) supertex inc. www .supertex.com
4 doc.# dsfp-hv7100 b072413 hv7100 reg v pp en uvlo gnd dac reg 3.3v v dd vgate lin ct rt out din0-3 powered by v dd - gnd vpp1 vpp2 ramp gen powered by v pp - v gate level translator ideal diodes functional block diagram functional description the hv7100 requires a single +16 to +75v supply to bias its internal circuitry. it internally generates 3.3v for v dd , and -12v relative to v pp for driving the external p-channel mosfet. if an external v dd is applied (greater than 3.6v but less than 5.5v), the internal regulator will shut off. the hv7100 drives an external p-channel fet to drive the 24v/48v dc fan. an external diode, connected across the fan terminals, is required to clamp the voltage across the fan to a diode drop during the off period. pulse width modulator the pwm circuit compares the internal triangle wave oscillator (0.5 C 2.5v pk-pk) with the linear control voltage or the dac output. its output is a square-wave pwm signal with duty cycle ranging from 0% to 100%. when an external pwm signal is applied to the enable input and the internal pwm generator is not needed, r t and lin should be connected to v dd and c t connected to gnd. oscillator a capacitor connected between the c t and gnd sets the frequency of the internal triangular frequency oscillator in conjunction with the timing resistor r t . r t sets the charge/ discharge current into and out of c t . the frequency is determined by the following equation: f = (0.258) (r t x c t ) p-channel gate driver the pwm output of the comparator circuit is level translated and is the input to the gate drive circuit. the gate drive circuit turns an external p-channel fet on and off by applying -12v and 0v (reference to v pp ), respectively, between its gate and source. the -12v supply to the gate drive circuit is generated internally from v pp . enable the en pin directly controls the gate drive circuit. pulling this pin to logic ground applies 0v to the external p-channel gate to turn it off. applying a logic high signal or pulling the voltage to v dd resumes the switching cycle of the pwm signal. speed control the fan speed can be controlled in three ways: linear control - applying a dc voltage between 0.5v to 2.5v to the lin pin varies the duty cycle of the voltage driving the fans from 0% to 100% according to: d = v lin - 0.25 2 linear control voltage below 0.5v will turn off the fan completely (0% duty cycle), while voltage greater than 2.5v will fully turn the fan on (100% duty cycle). supertex inc. www .supertex.com
5 doc.# dsfp-hv7100 b072413 hv7100 when using linear control mode, din0 C din3 should be set to logic 0. if desired, din may be used to set a lower limit on the fan speed. this input is immune to moderate noise on the control signal. digital control - applying logic signals to the din0 C din3 pins sets the duty cycle of the output. 0000 = 0% and 1111 = 100%. see table 1 for details. in digital control mode, lin should be set to 0v. din0 C din3 pins have internal pull downs so that the dac output will default to 0v when it is not used. external pwm - an external pwm signal can be applied to the enable pin to directly control the duty cycle. a logic 0 turns the transistor off, and a logic 1 turns it on. when using this control method, connect din0 C din3, lin, and r t to v dd . connect c t to gnd. the dac output and the linear control signals are ord together. whichever has the higher value dominates. this allows an analog temperature sensing circuit to override the digital inputs (din0 C din3) for added system protection. the following table illustrates the correlation between the digital inputs and lin voltage to the pwm duty cycle. table 1. dac signal and lin voltage to duty cycle programming. * guaranteed 0% @ 0000 and 100% @ 1111 din3 din2 din1 din0 lin gate drive duty cycle 0 0 0 0 0.500v 0%* 0 0 0 1 0.633v 6.7% 0 0 1 0 0.766v 13.3% 0 0 1 1 0.900v 20.0% 0 1 0 0 1.033v 26.7% 0 1 0 1 1.167v 33.3% 0 1 1 0 1.300v 40.0% 0 1 1 1 1.433v 46.7% 1 0 0 0 1.567v 53.3% 1 0 0 1 1.700v 60.0% 1 0 1 0 1.833v 66.7% 1 0 1 1 1.967v 73.3% 1 1 0 0 2.100v 80.0% 1 1 0 1 2.233v 86.7% 1 1 1 0 2.367v 93.3% 1 1 1 1 2.500v 100%* pwm fan drive v pp d3 en vgate out gnd vdd vpp1 hv7100 lin ct rt vpp2 v dd d2 d1 d0 when using direct pwm drive to the fans, it is best to set a low pwm frequency, in the range of 50hz -120hz. supertex inc. www .supertex.com
6 doc.# dsfp-hv7100 b072413 hv7100 v pp the addition of an lc low pass filter converts the pwm output to a dc voltage din0 ? din3 en vgate out gnd vdd vpp1 hv7100 lin ct rt vpp2 dc fan drive the hv7100 controls the fans with a pwm supply voltage. however, some fans require a steady dc voltage for proper operation. in order for these fans to function properly, an lc low pass flter should be added to cancel the pwm output to a steady dc voltage. the lc flter also provides another advantage. some fans draw large spikes of current during start-up and/or during normal operation. without the lc flter, these current spikes would be drawn directly from the +24 or +48v supply, caus - ing potential conducted emi problems. the lc flter prevents these spikes from occuring and/or reaching the +24 or +48v supply. v pp d3 en vgate out gnd vdd vpp1 hv7100 lin ct rt vpp2 v dd d2 d1 d0 setting a lower speed limit when using the linear control input, the digital control in - puts may be used to set a lower limit on the duty cycle. this is based on the fact that the higher control setting, linear or digital, dominates. in the example above, duty cycle is prevented from falling below 25% even if the linear control signal goes to 0v. supertex inc. www .supertex.com
7 doc.# dsfp-hv7100 b072413 hv7100 pin description pin # function description 1 vdd output of an internal linear voltage regulator, which in turn is powered by v pp . it provides power to the internal low-side (ground referenced) circuitry. an external voltage may be applied to this pin, provided it is higher than 3.6v but less than 5.5v. bypass this pin with a 100nf ceramic capacitor to ground. 2 lin a dc voltage ranging from 0.5 to 2.5v sets the duty cycle of the gate output from 0% to 100%. this input is immune to moderate noise on the control signal. 3 din0 applying 0000 to 1111 to these logic input pins sets the duty cycle of the gate output from 0 to 100%. a 1-bit increment is equal to 6.67% increment in duty cycle. see table 1 on page 5. 4 din1 5 din2 6 din3 7 en enable input. a logic high applied to this input enables the output. 8 gnd ground return for all the internal circuitry. this pin must be electrically connected to the ground of the power train and logic return. 9 ct in conjunction with rt, a capacitor from this pin to ground sets pwm frequency. a triangle wave appears on this pin, with an amplitude of 0.5 - 2.5v and at the pwm frequency . 10 rt in conjunction with ct, a resistor from this pin to ground sets pwm frequency. 11 vgate this is the output pin of the internal linear regulator that biases the gate drive circuit. bypass with 100nf ceramic capacitor to vpp. 12 vpp1 supply voltage pins. both must be connected to the supply voltage (+24v/+48v). connect together as close as possible to the ic. bypass locally with a ceramic capacitor to ground. 13 vpp2 14 out this pin is the output gate driver for an external p-channel power mosfet . supertex inc. www .supertex.com
8 hv7100 doc.# dsfp-hv7100 b072413 14-lead soic (narrow body) package outline (ng) 8.65x3.90mm body, 1.75mm height (max), 1.27mm pitch symbol a a1 a2 b d e e1 e h l l1 l2 1 dimension (mm) min 1.35* 0.10 1.25 0.31 8.55* 5.80* 3.80* 1.27 bsc 0.25 0.40 1.04 ref 0.25 bsc 0 o 5 o nom - - - - 8.65 6.00 3.90 - - - - max 1.75 0.25 1.65* 0.51 8.75* 6.20* 4.00* 0.50 1.27 8 o 15 o jedec registration ms-012, variation ab, issue e, sept. 2005. * this dimension is not specifed in the jedec drawing. drawings are not to scale. supertex doc. #: dspd-14soicng, version f041309. t op vi ew side vi ew vi ew a-a vi ew b a a seating plane 14 1 seating plane gauge plane l l1 l2 1 v iew b h h b a a2 a1 e e e1 d note 1 (index area d/2 x e1/2) note: 1. this chamfer feature is optional. if it is not present, then a pin 1 identifer must be located in the index area indicated. the pin 1 identifer can be: a molded mark/identifer; an embedded metal marker; or a printed indicator . supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. (website: http//www .supertex.com) ?2013 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com (the package drawings in this data sheet may not re?ect the most current speci?cations. for the latest package outline information go to http://www.supertex.com/packaging.htm l.)
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